The present invention relates to a semiconductor integrated circuit device to which a master slice system having a plurality of basic cells is applied and, more particularly, to a structure of the basic cell.
In this type of the conventional semiconductor integrated circuit device, the basic cells are arrayed in a predetermined pattern. Each of the basic cells is made up of COMSFETs and has a circuit arrangement as shown in FIGS. 1 and 2. The master slice system means a logic circuit forming technique in which, for a desired logic circuit formation, an interconnection pattern is selectively applied to a basic function logic circuit (referred to as a micro cell) consisting of small groups of basic cells arranged in a matrix fashion on a substrate. This will be explained in more detail.
In FIGS. 1 and 2, Q1 and Q2 designate respectively P channel MOSFETs. MOSFETs Q1 and Q2 are structurally arranged in opposition on a semiconductor wafer 1, and electrically connected in series with open gate electrodes. MOSFETs Q3 and Q4 are of N channel and structurally arranged in opposition on the wafer 1. These transistors are also connected in series, while being electrically open at the gate electrode. The transistors Q1-Q4 form a basic cell. A plurality of the basic cells, thus structured, are arrayed in a matrix fashion on the wafer 1. MOSFETs are selectively connected among the basic cells to form a desired logic circuit.
Another conventional basic cell is schematically and structurally illustrated in FIGS. 3 and 4. A group of P channel MOSFETs Q5-Q7 connected in series and another group of N channel MOSFETs Q8-Q10 are arranged in opposition on a semiconductor wafer 2. The gate electrodes MOSFETs Q5 and Q8, Q6 and Q9, and Q7 and Q10 are interconnected with each other, as shown. As in the FIG. 1 case, the basic cells are arranged in a matrix fashion. These MOSFETs are selectively interconnected among the basic cells, thereby to form a logic circuit.
FIG. 5 shows an exclusive OR gate as an example of the micro cell, which is constructed by using the basic cells shown in FIGS. 3 and 4. The exclusive OR gate is expressed by a symbol shown in FIG. 6. The exclusive OR gate is also expressed by a combination of logic gates, two NOR gates 12 and 13, and an AND gate 4, as shown in FIG. 7. In FIGS. 5-7, A and B designate input signals, and Z designates an output signal. V.sub.DD designates a power potential, and GND designates a ground potential. In the gate circuit of FIG. 5, 11.sub.1 and 11.sub.2 stand for basic cells. As shown, P channel MOSFETs Q11-Q13 in the basic cell 11.sub.1 are connected in series with P channel basic cells Q21-Q23. Similarly, N channel MOSFETs Q14-Q16 in the basic cell 11.sub.1 are connected in series with N channel MOSFETs Q24-Q26 in the basic cell 11.sub.2. The groups of the transistors Q11-Q13 and Q21-Q23 are oppositely arranged with each other on a semiconductor wafer, and the groups of N channel MOSFETs Q14-Q16 and Q24-Q26 are likewise oppositely arranged. The MOSFETs Q11-Q16 and Q21-Q26 are selectively interconnected. In the model pattern of FIG. 5, circles indicate contact portions necessary for forming a semiconductor device as a product, while black dots indicate contact portions necessary for forming the circuit of FIG. 7.
In the conventional semiconductor device to which the master slice system is applied, MOSFETs constituting each basic cell are designed with the equal dimensions. The size of the MOSFETs is standardized. The standardization enables a designer to flexibly design various types of logic circuits in a computer aided design (CAD). The number of loads and gate circuits, which result from the interconnection wires, is different with the type of logic circuit. Allowing this, the size of the MOSFET is satisfactorily large so as to be adaptable for a logic circuit requiring a large drive ability. In other words, the MOSFET is designed to have a satisfactorily large mutual conductance "gm". However, the size of this is usually much larger than that of the least required. Thus, in the conventional semiconductor devices, the size of the MOSFET used is relatively large. This indicates that the packing density is low.
Further, when MOSFETs with many different "gm rates" are required for the N channel and the P channel MOSFETs, various MOSFETs must be used. This is undesirable from the viewpoint of circuit design and applications of the circuit elements.